Another method of logic synthesis of digital counting circuits

Abstract

In order to synthesize automat (in this case digital counters), the minimizing internal states is of particular significance and plays a decisive role in the results of synthetic circuit. This can be done in many ways, but the use of Karnaugh map is considered optimal. However, this process has some disadvantages that it can not be overcome when the number of input variants is large. In experience, if the number of variants is 7, manual minimization of circuit functions using Karnaugh map arises many difficulties and even become impossible if over 10 variants are available. In order to deal with this weakness, it is both necessary and rational to use computer in logical synthesis of counting circuit. This is the aim of this article.