| dc.contributor.author | Nguyen, Quy Thuong | |
| dc.date.accessioned | 2011-06-08T17:04:42Z | |
| dc.date.available | 2011-06-08T17:04:42Z | |
| dc.date.issued | 2010 | |
| dc.identifier.citation | 55-58 | vi |
| dc.identifier.issn | 0866-8612 | |
| dc.identifier.uri | http://tainguyenso.vnu.edu.vn/jspui/handle/123456789/12348 | |
| dc.description.abstract | It is not easy to point out Hazards and Deadlock in a circuit with a complex structure. Determination methods for Hazard, Race, Deadlock in [1-3] cannot be applied to this case. With complex circuit structure, specific solution must be offered for each circuit type such as solution of synchonization for asynchronous circuits [4]. GALS circuit is a complex circuit system; thus, the above-mentioned solution is also applied to this circuit | vi |
| dc.language.iso | en | vi |
| dc.publisher | Tạp chí Khoa học | vi |
| dc.title | Verification of hazard, race and deadlock in GALS-circuit | vi |
| dc.type | Article | vi |
| Files | Size | Format | View |
|---|---|---|---|
| 8.pdf | 95.75Kb |
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