2009 International SoC Design Conference, ISOCC 2009
Citation:
Page : 520-523
Abstract:
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been
developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the
multiplied clock signals ranging from 125MHz to 2GHz. In addition, thanks to the proposed anti-harmonic
lock block, the clock generator can change the frequency dynamically in one cycle time of the reference
clock. The proposed DLL-based clock generator occupies 0.019mm2 and consumes 21mW at 2GHz. The
ratio of power consumption to frequency of the proposed clock generator is smaller than those of
conventional ones. ??2009 IEEE.
