2009 International SoC Design Conference, ISOCC 2009
Citation:
Page : 512-515
Abstract:
This paper introduces the 10b 1MS/s 0.5mW SAR ADC with double sampling technique. It
utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M
65nm technology and occupies 0.111um 2. The maximum sampling rate is 1MS/s. The simulated SNDR and
SFDR are 55.6dB and 62.7dB, respectively at input frequency of 484kHz. Power consumption of the data
converter is total 507uW with 1.2-V supply. ??2009 IEEE.
